BittWare Announces SmartNIC Shell for Building FPGA-powered 100G NICs

SmartNIC Shell Supports DPDK, Xilinx SDNet, P4 Programming, User Customisations, and Timestamping

BittWare has announced SmartNIC Shell, a suite of IP modules for building 100G network interface controllers (NICs) using FPGAs for hardware packet processing.

Users can fully customise Shell components, including a Match/Action pipeline with features including Xilinx SDNet support and the P4 network programming language. For host application interaction the Arkville DPDK IP is integrated for kernel bypass. SmartNIC Shell allows teams to avoid the time-consuming process of building core NIC functions into an FPGA, allowing them to focus resources on their own application.

Read more - Full Press Release

“We built the SmartNIC Shell because we noticed that many of our customers spend half their development time creating a networking shell,” said Craig Lund, Vice-President Network Products, BittWare. “All of that development time should be going into their own product’s unique value instead.”


SmartNIC Shell Top Features

Quickly Build 100G NICs	Focus your attention on your unique application, instead of re-inventing a NIC.
Match/Action Pipeline	Standardised kernel bypass for host interaction over PCIe. SmartNIC Shell provides DPDK offload to interact with host applications.
TimeServo Timestamping	Precision time stamping including 1588-compatible clock adjustments. Uses TimeServo IP from Atomic Rules
Xilinx UltraScale+ FPGA	Large, powerful FPGAs with ample room for user IP. Selection of BittWare boards including traditional low-profile NIC size (XUPPL4) to 3/4-length boards with additional logic and memory options (XUPP3R).

For more information please contact the Sarsen FPGA team on +44 1672 511166 or send us an email - info@sarsen.net

White Paper - Intel Stratix 10 MX Devices Solve the Memory Bandwidth Challenge

White Paper

Intel® Stratix® 10 MX Devices Solve the Memory Bandwidth Challenge

Intel has put together a new White Paper to explain how the brand new Intel Stratix 10 MX family will help customers efficiently meet their most demanding memory bandwidth requirements.

"Conventional memory solutions have limitations that make it difficult for them to meet next-generation memory bandwidth requirements. This white paper describes the emerging memory landscape that addresses these limitations.

The Intel® Stratix® 10 MX (formerly Altera® Stratix 10 MX) DRAM system-in-package (SiP) family combines a 1 GHz high-performance monolithic FPGA fabric, state-of-the-art Intel Embedded Multi-die Interconnect Bridge (EMIB) technology, and High Bandwidth Memory 2 (HBM2), all in a single package. The Intel Stratix 10 MX family helps customers efficiently meet their most demanding memory bandwidth requirements, which are not possible using conventional memory solutions.

This white paper describes the solution and explains how Intel Stratix 10 MX devices solve the memory bandwidth challenge for key end markets and applications."


Authors
Manish Deo
Senior Product Marketing Manager
Intel Programmable Solutions Group

Jeffrey Schulz
In-Package I/O Implementation Lead
Intel Programmable Solutions Group

Lance Brown
Senior Strategic and
Technical Marketing Manager
Intel Programmable Solutions Group

© 2017 Intel Corporation. All rights reserved.

In Case You Missed It... DSEI 2017

Sarsen Technology exhibited in the dedicated Security Zone at DSEI 2017, showcasing the some of the worlds highest-performance computing hardware from some of our international manufacturers..

We were joined by Ken Sheth and Tony Barbieri from EIZO Rugged Solutions who were running a very cool interactive GPGPU CUDA demo, based on the new Condor GR3 3U VPX single board computer.

Kerry Howell and Gary Harris from VersaLogic were also with us on the stand and introduced their brand new Ethernet over Fibre mini PCIe module which was very popular. VersaLogic's family of rugged, embedded computers were on display, including a special focus on the modules with a Trusted Platform Module (TPM), including the new Raven and Liger boards.

If you stopped by the stand you would have seen a number of 1553 and ARINC boards from Alta Data and a wide range of rugged SBCs from Extreme Engineering, including the XPedite8150 COM Express Module based on the Intel Atom E3800 'Bay Trail' series of processors. We also had a lot of interest in the PCIe boards from BittWare, featuring both Xilinx UltraScale and Intel Arria 10 and Stratix V FPGAs.

If you didn't make it to DSEI this year but you'd like some more info on the technology we were talking about at the event please get in touch - info@sarsen.net

 

ISC High Performance 2017 - Meet with BittWare and Sarsen Technology

Event: ISC 2017
Date: Sunday 18 June - Thursday 22nd June
Location: Frankfurst, Germany
Stand: A-1431

ISC High Performance is an international event for academic, industrial and commercial disciplines to come together and share ideas and knowledge across the entire high performance computing spectrum.

The 2017 conference offers 3 days of speakers and seminars based around this years focus topics:

HPC Systems	HPC Applications & Algorithms	HPC Trends & Challenges
Exascale System Developments (Architecture & Concepts)	Life Sciences	High Performance Visualization
Processor Technologies for HPC and AI	Energy Exploration	Big Data Experiments & Big Data Analysis
Memory Outlook	Turbulences & Combustion	Quantum Annealing for Combinatorial Optimization Problems
Interconnects for HPC Systems	Advanced Material Science
Programming Models (Concepts for Exascale)	Algorithms for Extreme Scale in Practice
	Large Scale Engineering & Cloud Computing

Sarsen Technology works with BittWare to provide customers with high-performance FPGA solutions based on Intel Stratix 10/Arria 10 and Xilinx UltraScale/UltraScale+ FPGAs, for data centres, network packet processing and cyber security applications.

Sarsen Technology is exhibiting at ISC 2017 alongside BittWare and EMG2, you can find us at stand A1431. BittWare’s range of Intel and Xilinx FPGA PCIe boards will be on display, along with live demos including Deep Learning with their OpenCL Board Support Package and 100 GbE packet processing with Intel’s DPDK.

For more information please contact Sarsen Technology.

BittWare Acquires nCk Research and Forms Network Products Group

BittWare has announced the acquisition of nCk Research, a network solutions provider with a portfolio of FPGA intellectual property (IP) designed for BittWare’s PCIe boards.

nCk’s staff joined BittWare as employees under a newly-formed Network Products group. Craig Lund, formerly with CSPI-Myricom, will lead BittWare Network Products as V.P. and General Manager.

www.bittware.net


The new group’s first product, based on nCk’s groundbreaking IP, was recently announced at the RSA Conference in San Francisco. The StreamSleuth is a network packet processing appliance, providing Xilinx UltraScale+ FPGA-based accelerated monitoring, filtering, and routing at 100 GbE line rate.

“Building on the recent success of our horizontally-focused FPGA Platform business and the acquisition of nCk, it is huge step for BittWare to launch a vertically-focused network solutions group,” said Jeff Milrod, President & CEO of BittWare. “The addition of Craig’s leadership and extensive history of successfully driving new technology into emerging markets makes me confident that we will be able to quickly combine our world-class FPGA platforms with our innovative IP to deliver compelling network products to a market desperate for 100 GbE solutions.”

nCk Research had initially chosen BittWare’s FPGA solutions for prototyping their 100 Gbit/s IP. The unique approach and features of the IP so impressed BittWare that a collaboration was formed to accelerate the product development time. This grew into a need for closer access to BittWare’s software and hardware engineering teams, resulting in the acquisition in the second half of 2016.

Craig Lund joined BittWare in January, 2017 as V.P. and General Manager of the newly-formed Network Products group. Craig’s extensive knowledge of the capabilities—and limitations—of today’s high-speed network hardware and software plus his decades of experience leading teams in product development ensures the products BittWare creates are a match for the real-world needs of sophisticated, high-end network users.

BittWare Set To Launch New Networking Product at RSA 2017

StreamSleuth from BittWare is a brand new 100GbE packet processing appliance with a pre-programmed FPGA that performs hardware accelerated network packet processing at line rate.

• Use modes include packet broker, active monitor, or supplemental firewall.

• Users configure the device with a web-based GUI or API - no FPGA programming required!

StreamSleuth is the first product from the new BittWare Network Products group, focused on high-performance networking products.

You can meet with the BittWare team at the RSA Conference, Stand S312 - 13-17 Feb

RSA Conference
The current state of cybersecurity means there are many opportunities for the industry as a whole to collaborate on new innovations. Discovering the next great opportunity will require everyone to embrace new and unique perspectives from a broadly diverse base of people and sources.

RSA Conference’s mission is to connect you with the people and insights that will empower you to stay ahead of cyber threats.

For more information please contact Sarsen Technology on +44 1672 511166 or send us an email - info@sarsen.net

BittWorks II Toolkit - Is it Even Necessary for my FPGA Development?

What is a Software Toolkit? 
Putting it simply, a software development toolkit is a set of tools that provides an interface between a hardware platform and a host system. Toolkits are critical if you want fast time to market. This is especially important for BittWare customers...

Why do I Need One?
BittWare has leveraged years of experience to provide a solid base for developers to make a start on their application, and the Toolkit has been an integral part of existing customer's success. They have been able to see first hand the value of the BittWorks tools, because they are so critical in getting projects up and running quickly. This software allows BittWare to properly support our customers.

More: BittWorks Toolkit

The BittWorks II Toolkit is a suite of development tools for BittWare’s FPGA-based hardware. The Toolkit includes drivers, libraries, utilities, and example projects for accessing, integrating, and developing applications for the BittWare board. Utilities and drivers connect the board to the host via PCIe, USB, Ethernet, or serial port, and provide easy access to the board’s system monitoring features and Flash programming.

Extensive libraries provide a consistent, intuitive API for integrating the board into the system and example projects illustrate data movement and provide a starting point for development. The Toolkit supports 64-bit Windows and Linux platforms and is tightly integrated with BittWare’s FPGA Development Kit (FDK), which provides FPGA board support IP and integration for BittWare’s FPGA-based boards.

The Nerdy Stuff
The BittWorks II datasheet is a great tool and clearly outlines what is provided and how it can help you get your application up and running quickly.

View Datasheet

Do I Need To Pay For It?
Well, yes. But BittWare doesn't currently charge for support (unlike some of the other board manufacturers in this market space) and this is only possible because of the development tools available. If a developer has the BittWorks Toolkit BittWare are able to provide the utilities they need to use the board as well as provide known working examples for the customers to leverage.

Toolkit licenses are handled per project/per location.  For a single project at one location there is a maximum of 3 licenses to be purchased. This means is that if there are 10 developers working on Project X you only need to buy 3 licenses.

Tell Me More...
If you'd like more information on how the BittWorks Toolkit and FDK can help speed up your development on both Intel (Altera) and Xilinx FPGA based hardware please get in touch with one of our specialists: info@sarsen.net

PCIe Board with Intel (Altera) Arria 10 GX FPGA Machine Learning Demonstration

BittWare took part in Super Computing 2016 last week, and used the event to showcase their must-see FPGA demos in network packet processing (NPP) and high-performance computing (HPC). If you were at the show you will also have seen BittWare's wide range of the latest Intel (formerly Altera) and Xilinx FPGA-based boards on display.



One of the demonstrations featured BittWare’s A10PL4 board, using Intel’s deep learning IP core loaded on the Arria 10 FPGA.

The A10PL4 from BittWare is an Altera Arria 10 FPGA PCIe board offering plenty of high speed serial I/O interfaces and debug support. Two QSFP cages are available, both connected to the Arria 10 FPGA removing latency in the external PHYs. The A10PL4 supports up to 32GB of DDR4 as well as flash memory with factory default and support for multiple FPGA images.

Find out more - A10PL4

 

Machine Learning

'Machine Learning' is based on the development of computer programs that can learn and create their own rules. In deep learning, a task can be learned by the machine from a vast amount of data, either in supervised or unsupervised manner.

With the Deep Learning IP customers can leverage Intel Caffe in the Data Analytics Acceleration Library (DAAL) and Intel MKL-DNN to build AlexNet- or GoogleNet-like topologies without requiring a recompilation of the FPGA.

Accelerating machine learning applications like these are an excellent fit for FPGAs and OpenCL. Up to 16 A10PL4s can be combined inside a 4U server for a total of 18M logic elements and 512 GBytes of DDR4 memory.

Find out more - Terabox

For more information please speak to one of our FPGA specialists - +44 1672 511166 or send us an email - info@sarsen.net 

www.sarsen.net

Join us at the next FPGA Network meet-up on Tuesday 11th October in Swindon!

FPGA experts who care about tools and methodologies can’t afford to miss the next meeting of the NMI FPGA Network... You will find this meeting especially compelling if you are an architect, designer, verification specialist, project manager or engineering manager.

We know how important design tools and methodologies are in creating better FPGA designs and FPGA systems-based, this is why we are excited to be sponsoring this event and would be delighted to see you there too!

On the day we will contribute to the debate with a discussion on ‘FPGA Platform Development Kit Enables Fast TTM’ delivered by Chad Hamilton, VP of Intellectual Property (IP), Software and Support at BittWare.

Chad will join the discussion along with FPGA specialists from other Industry leaders.

Confirmed Speakers 
Synopsys: Flexible debug and visibility techniques to enhance all FPGA design and deployment cycles
BittWare: FPGA platform development kit enables fast TTM
Mentor Graphics: Staying competitive by evolving your FPGAverification methodologies
Bitvis AS: A game changer for VHDL verification: advanced VHDL verification – made simple for anyone
Telexsus: FPGA real-time debug with vastly increased operational capture time – live demo
Cadence: 100M gate designs in FPGAs – fact or fiction?
Altera now part of Intel: Zen and the art of high-speed design
Xilinx: Vivado HLx Design Methodology
ITDev: Static code analysis using Blue Pearl software

See full details (pdf)

We are also very pleased to have Manuele Papais from DAVE Embedded Systems with us, showcasing their Xilinx Zynq based hardware and talking to engineers about Asymmetric Multi Processing on Cortex-A CPU: system integrity and reliability on Linux and RTOS cores.

Find out more and book your place here.

We look forward to seeing you at the FPGA Network Event ‘Design Tools and Methodologies’!

BittWare Releases Arria 10 OpenCL BSPs for Altera OpenCL SDK 16.0.2 Release

BittWare has recently announced the availability of Arria 10 FPGA Board Support Packages (BSPs) for Altera's recently released OpenCL SDK 16.0.2, including support for production silicon.

See full press release

BittWare’s OpenCL BSPs allow customers to develop applications for the Altera Arria 10 1150GX FPGA using OpenCL quickly and easily. OpenCL makes FPGA development much simpler by enabling designers to code their systems and algorithms in a high-level C-based framework, directly generating FPGA programming files from a pure software development flow.

FPGAs can dramtically improve speed and increase responsiveness for many system designs, in markets as diverse as defense/aerospace, fintech and life sciences. BittWare offers BSP variants to support High Performance Computing (HPC) as well as Network Processing applications.


"We've worked closely with Altera to ensure that our OpenCL BSPs provide the best quality results possible," said Chad Hamilton, BittWare VP of IP, Software & Support. "For those customers who prefer to code in a C-based framework, our OpenCL BSPs provide the tools necessary to get them up and running quickly and efficiently."

OpenCL Developers Bundle
The BittWare OpenCL BSPs are included in the OpenCL Developer’s Bundle, which includes a BittWare Arria 10 or Stratix V PCIe board, the BittWorks II system development software, the Altera Quartus II soft­ware, and the Altera SDK for OpenCL. This competitvely priced development bundle gives developers access to the latest generation of high-performance FPGAs on a validated PCIe board, while also significantly reducing their time ­to market by using OpenCL to develop their application.

Benefits of OpenCL for FPGAs

• Faster time-to-market using the OpenCL C-based parallel programming language as opposed to low-level hardware description language (HDL)
• Quick design exploration by working at a higher level of design abstraction
• Easy design re-use by re-targeting existing OpenCL C code to current and future FPGAs
• Faster design completion by generating an FPGA implementation of OpenCL C code in a single step, bypassing the manual timing closure efforts and implementation of communication interfaces between the FPGA, host, and external memories.
• Increased performance by offloading performance- intensive functions from the host processor to the FPGA
• Significantly lower power than a GPU or multicore CPU by using the Altera SDK for OpenCL, which generates only the logic needed

Intel Developer Forum - 16th-18th August 2016

The Intel Developer Forum offers everything you could possibly need to make sure you're at the forefront when it comes to the latest technology.

As well as a world class forum schedule, including a keynote address from Brian Krzanich, the Technology Showcase offers you unprecedented access to the world’s most exciting products. You'll have the opportunity to ask your toughest questions, or find an ingenious solution to your design challenges.

Ready to meet you at the IDF will be the team from Extreme Engineering Solutions (X-ES). You will find them on stand #730, where you'll be among the first to see the latest and greatest embedded boards and solutions, based on Intel's Xeon D, Atom E3800 and Core i7 processors.

Click the button to find out more about the rugged Intel-based boards from X-ES.

___________________________________________________________________________________________________

With the acquisition of Altera by Intel, the Altera SoC Developer Forum (ASDF) is now the Intel SoC FPGA Developer Forum (ISDF). ISDF is dedicated to the technology and application of SoC FPGAs across a wide range of design areas, including networking and communications, data centre and cloud computing and the Internet of Things (IoT).

The theme of this year's event is Acceleration:

• Accelerate your design - with hardware acceleration in SoC FPGAs
• Accelerate your development process - with leading edge design tools and ecosystem support
• Accelerate your learning - by attending ISDF 2016

The ISDF16 event is taking place on day 3 of the Intel Developer Forum, and our friends at BittWare will be there showcasing the new Altera Arria 10 PCIe board platforms alongside their OpenCL solutions, including the popular OpenCL Bundle . The bundle includes a BittWare Arria 10 or Stratix V FPGA-based PCIe board, board support package, BittWorks II Toolkit-Lite system development software, Altera Quartus II software, and the Altera SDK for OpenCL.

For more information about the IDF, ISDF or any of the products from BittWare or X-ES please get in touch with the Sarsen Technology engineering team on +1672 511166 or send us an email - info@sarsen.net

NMI FPGA Network: Design Tools and Methodologies - 11th October 2016

The National Microelectronics Institute (NMI) was created to increase the quality and quantity of electronic engineering and manufacturing in the UK.

NMI provides:

• A focal point for this industry; connecting industry, academia and stakeholders to build a strong eco-system
• A mechanism to work together to address common challenges in engineering and manufacturing sharing domain knowledge and know-how across vertical applications
• Opportunities to raise your profile and develop your business through new partnership and programs addressing business opportunities
• This industry with a voice by building industrial coherence on the strategic issues and opportunities; seeking to inform government and its agencies; supporting their decision-making processes
• A response to your individual business needs

NMI Infographic – Click to view full size

FPGA Network – Design Tools & Methodologies

On October 11th the NMI is hosting an event in Swindon which will allow members to share experiences of how FPGA design tools and methodologies impact build schedules, solve difficult problems, affect quality, optimise architecture and bridge hardware and software communities.

This event is ideal for you if you are an architect, designer, verification specialist, project manager or engineering manager and you care about tools and methodologies to help do a better job of creating FPGA designs or systems based on FPGAs.

Confirmed Speakers:

Synopsys: Flexible debug and visibility techniques to enhance all FPGA design and deployment cycles  
Mentor Graphics: Staying competitive by evolving your FPGA verification methodologies
Cadence: 100M gate designs in FPGAs – Fact or Fiction?  
BittWare: FPGA Platform Development Kit Enables Fast TTM  
Telexsus: FPGA real-time debug with vastly increased operational capture time – live demo  
Altera (now part of Intel): Zen and the art of high speed design

We have 5 free tickets for this event. If you'd like to join us please contact Sarsen Technology to register your interest - info@sarsen.net

EE Journal Feature Article - The x86 Moat: Can Intel Defend the Data Center?

A Data Centre is a dedicated space for housing computer systems and associated components,

including telecoms and storage systems. Data centres stem from the days of the huge computer rooms of the early ages of the computing industry. This arrangement was largely unaffected by the steady reduction in size of the computer as the functionality requirements increased to such an extent that the systems still required the same amount of space. 

During the 1990s, the challenge was deploying enough processing power to meet the rapidly growing web audience. Considering Intel's market share for this industry today, x86-based servers didn't actually exist until the late 90s. But within a decade x86 processors were in the majority of servers being deployed in data centres.


Kevin Morris has written a really interesting article for EE Journal, looking at the role of FPGAs and their potential impact on the EDA industry.


May 31, 2016
The x86 Moat - Can Intel Defend the Data Center?
By Kevin Morris

Read the full article 

Excerpt:

Intel’s data center fortress is defended by the x86 moat.

The single factor that most locks Intel’s hardware into the sockets that sit on the blades that slip into the racks that line the rows of just about every data center on the planet is the x86 moat. Just about every piece of software in the universe was written and optimised for the x86 architecture. There are billions and billions of lines of code out there working every day that have been debugged and tested and proven to work reliably (well, as reliably as software gets, anyway) on Intel’s architecture.

Before any attacker can hope to displace the incumbent supplier, they have to convince the customer that changing processor architectures is really not that big a deal.

Well-designed fortresses are very good at protecting against the expected. For the fortress to be truly at risk - for Intel’s position in the data center to be realistically challenged in a meaningful way - we would need to see a sea change - an event that profoundly alters the nature of the game - a discontinuity.

FPGA-based acceleration is that discontinuity.

If the creation of heterogeneous processors with von Neumann machines sharing the workload with FPGA-based accelerators can improve energy efficiency in the data center by orders of magnitude, we have a compelling event worth an incredible amount of money - and trouble.

End of excerpt


FPGA Hardware
Sarsen Technology supplies and supports a wide range of hardware based on both Xilinx and Altera FPGAs, and can also supply a full range of software development tools and software drivers to get your FPGA system to market on-time and on-budget - www.sarsen.net
For more information please contact Sarsen Technology on +44 1672 511166, or send us an email: info@sarsen.net

BittWare Announces OpenPOWER CAPI DevKit for Xilinx FPGA-Enabled Accelerator Cards

FPGA platform supplier provides CAPI enabled FPGA accelerator cards for POWER8 processors.

April 2016

BittWare, an industry-leading board supplier for over 25 years, announced today an OpenPOWER CAPI Developer’s Kit for its Xilinx FPGA-enabled accelerator cards. Providing a fast, efficient way to connect the Xilinx All Programmable FPGA to a CAPI-enabled IBM POWER8 system, the developer’s kit includes the FPGA accelerator card, IBM Power Service Layer (PSL) IP to provide the connection to the POWER8 chip, CAPI host support library, and an example CAPI design.

The FPGA accelerator card included in the kit is BittWare’s XUSP3S, which is a ¾-length PCIe board featuring the Xilinx Virtex® UltraScale™ VU095, four QSFPs for 4x 100GbE, and flexible memory configurations with up to 64 GBytes of memory and support for Hybrid Memory Cube (HMC).

Most FPGA accelerators use PCIe to connect to the host processor unit. IBM has developed CAPI (Coherent Accelerator Processor Interface) as an alternative that takes some of the overhead and complexity out of the I/O subsystem by providing a direct interface between the host and the FPGA. Developers can run their specific FPGA solutions as a peer to the IBM POWER8 cores, enabling higher system performance with less programming complexity.

“BittWare is pleased to work with Xilinx and IBM to offer CAPI enabled FPGA acceleration platforms for POWER processors,” said Ron Huizen, VP of Systems and Solutions at BittWare. “Our XUSP3S board is a compelling option for data center applications, and with the addition of CAPI will now allow our customers to develop their applications even more quickly and efficiently.”

“CAPI on POWER8 systems provides a high-performance solution for implementing customer-specific, computation-heavy algorithms on an FPGA,” said Sumit Gupta, VP, High Performance Computing & Data Analytics at IBM. “The IBM solution enables higher system performance with a much smaller programming investment, allowing hybrid computing to be successful across a much broader range of applications. BittWare’s CAPI support brings this innovation to an even wider range of customers.”

“The demand for FPGA acceleration in data centers is increasing, and with that the need for innovative, high performance accelerator solutions,” said Curtis Pulley, data center business manager at Xilinx. “The CAPI-enabled Xilinx FPGA-based offerings from BittWare are a great addition to the OpenPOWER ecosystem and extend our efforts to deliver industry-leading solutions for IBM POWER systems.”

Availability
BittWare’s OpenPOWER CAPI Developer’s Kit will be available in early Q2 2016. Contact Sarsen Technology for details.



About OpenPOWER

BittWare is a member of the OpenPOWER Foundation, an open development community based on the POWER microprocessor architecture. The Foundation includes a growing roster of technology organizations working collaboratively to build advanced server, networking, storage, and acceleration technology as well as industry-leading open source software aimed at delivering more choice, control, and flexibility to developers of next-generation, hyperscale, and cloud data centers. The group makes POWER hardware and software available to open development for the first time, as well as making POWER intellectual property licensable to others, greatly expanding the ecosystem of innovators on the platform.

To learn more about OpenPOWER and to view the complete list of current members, go to www.openpowerfoundation.org.

About BittWare, Inc.

For over 25 years, BittWare has designed and deployed high-end network processing, signal processing, and high performance computing platforms that significantly reduce technology risk and time-to revenue for our OEM customers. Our products utilize the latest FPGA technologies on industry-standard COTS form factors, including PCIe, and are available either as boards or in systems. We also provide a great deal of value-add with IP, software, support, and services. When customer requirements make it difficult to use industry-standard boards, BittWare can provide modified solutions and/or licensed designs. For more information on BittWare and its innovative FPGA platform solutions, visit www.bittware.com/xilinx.

Learn more: Find your solution... Built on BittWare.

BittWare and nCk Research Collaborate to Provide an FPGA-based 100G Network Packet Broker with PCAP Filtering

As one of the market leading manufacturers in their field, new announcements from BittWare are always exciting...

The latest from the BittWare team in Concord, NH, is a collaboration with nCk Research - an innovative supplier of FPGA IP. This dream team have worked together to come up with a 100G network packet broker with PCAP filtering, which is implemented on BittWare's new PCIe board featuring Xilinx's UltraScale Virtex FPGA.

BittWare XUSP3S - Xilinx UltraScale 3/4-Length PCIe Board with Quad QSFP, DDR4, QDR-IV, and QDR-II+

PCAP processing expressions are used by many packet broker systems, but the point-to-point fabric from nCk Research is the first in the industry to optimise user inputs before loading resource settings into registers in the FPGA. This optimisation allows more rules to be packed into a smaller space and increases packet processing efficiency. The packet broker IP also provides configurable support for RMON1, line rate policies, aggregation, decimation, and de-duplication.

The XUSP3S is backward compatible with 10G/40G, and with nCk's IP supports up to 4x 100G ports and/or up to 16x 10/25G ports on each board. It can also be configured to implement any combination in between, allowing users to deploy with some 10G today and easily upgrade to all 100G in the field.


"We're pleased to be able to work with nCk to add innovative and comprehensive application IP to our already well established FPGA platforms," said Ron Huizen, Vice President of Systems & Solutions at BittWare.
"Their advanced filter IP component lets programmers use standard PCAP syntax to filter packets at full 100G line rate, and they can modify the filters on the fly- without having to reconfigure the FPGA. This, combined with nCk's other packet processing IP running on the most advanced FPGAs in the world, creates a compelling solution."


"FPGAs are the ideal choice for 100G at full line rate, and we're pleased to be able to partner with BittWare to build on their best-in-class FPGA platforms," said Matthew Chabot, President of nCk Research. "Their XUSP3S UltraScale board with support for quad 100G is a perfect fit."

Learn more:
10/25/40/100G Ethernet Filter IP Core for FPGA 
10/25/40/100G Packet Broker with PCAP Filtering 



Terabox
Up to 8 XUSP3S application cards can be installed in a BittWare TeraBox 4U rackmount system to handle up to 32x 100G ports and/or up to 128x 10/25G ports, allowing users to build virtually any packet processing solution with nCk network IP libraries; coupled with an optional PCIe DMA or NIC interface, it becomes possibly the most feature rich packet processing appliance in the industry.

Packet Broker with PCAP Filtering IP & Appliance Pricing and Availability
This configuration is available for purchase now, please contact Sarsen Technology for more information.

NMI Event - “Managing FPGA Projects: A Cat-herders Guide” - November 25th 2015

Sarsen Technology is taking part in the “Managing FPGA Projects: A Cat-herders Guide” event next week, organised by NMI.

About NMI



Agenda items include:

“Leveraging ASIC and Software methodologies for FPGA design” – Leon Wildman – Aptcore

“Managing complexity: version control basics for FPGA projects” – Sven-Erik Knop – Perforce

“Teaching an old dog new tricks – The opportunities and resulting challenges of getting consumer silicon into safety critical systems” – Mike Allen, Jon Wright – GE Avionics

“Management sans frontiers: Removing the roadblocks in FPGA projects” – Chris Higgs – Potential Ventures

“Optimizing the HW/SW partition of complex embedded systems” – Simon George – Xilinx

“Inspiring the next generation of FPGA engineers: Skills management in the long term” – Jeremy Bennett – Embecosm

“Requirement driven development for safety-critical applications” – Alex Grove – FirstEDA/Aldec

“Applying Agile Techniques to FPGA Projects” – Nigel Elliott – Mentor Graphics

. . . plus an open discussion to share hints and best practices.

Sarsen will be showcasing Altera and Xilinx FPGA-based hardware from BittWare, Extreme Engineering and DAVE Embedded Systems, as well as C to FPGA software for Xilinx and Altera FPGAs from Impulse Accelerated.

REGISTER NOW

Registration is now open, so please join us to learn some new tips, tricks and “agile” methods that teams are using in order to keep on top of ever-more complex FPGA designs.

UPCOMING EVENTS!

Sarsen Technology takes part in various events throughout the year across a number of markets and technology sectors, sometimes as a visitor and quite often as an exhibitor. This is just a snapshot of our upcoming events, so if you would like more information please contact Laura Biddiscombe for details.

• June 9th - VentureFest, Bristol - A one-day event showcasing Bristol and Bath’s most innovative and enterprising companies and start-ups. This is a free event, however you will need a ticket.


• June 17th -  NMI Model Driven Engineering 2015 - As a member of NMI we get access to some great events. This one, held at Thales in Crawley, is mostly focussed on electronics and software domains, reflecting the interests of NMI members and guests.


• September 15th-18th - DSEI 2015 - DSEI brings together the entire defence and security industry to source the latest equipment and systems, develop international relationships, and generate new business opportunities. Sarsen Technology will be exhibiting within the UK Pavilion on stand S4-453, where you can see an exciting range of embedded technology from BittWare, Ecrin Systems, Extreme Engineering, General Standards and Tech Source.


• October 21st - 22nd - Embedded Design Show 2015 - Following last years' successful exhibition we are pleased to once again be taking part alongside the team from DAVE Embedded Systems. You can find us on Stand G32, where we will be showcasing the complete range of SoMs from DAVE Embedded Systems, based on FPGA technology, ARM Cortex-A architecture, Freescale and Texas Instruments processors and Xilinx SoC.

Industry Article - How to evolve a risk-based FPGA strategy into a value add strategy

Fixnetix is a leading managed service provider for the global financial community, with a team of highly skilled professionals tasked with developing and providing dynamic products and solutions to meet the ever changing requirements of the banking industry.

Dr Marcus Perrett, Director of Technology and Development, provides an insight into the use of FPGA technology in the finance industry.

How Fixnetix has evolved their risk-based FPGA strategy into a value add strategy 

The use of FPGAs in finance was originally driven by regulation. Brokers were encouraged (or mandated by regulation) to have controls in place to monitor and, if required, cancel or stop clients trading. As clients had traditionally enjoyed direct access to the market via a broker, a system that was positioned between a trading system and the exchange needed to be a fast as possible to reduce the impact to a client’s trading strategy. Hence, FPGA technology was employed to great effect in a number of configurations; some banks built their own systems and several vendors built their own.

Fixnetix has enjoyed success using that model in Canada, where regulation has driven the need for a low latency risk solution for latency sensitive clients trade flows via a broker.

However, regulation alone has not proven to be the only driving factor for the use of FPGA in the finance area. For example, in Japan, the native exchange (TSE) utilises a complex and verbose protocol called arrowhead. In addition, the rules around erroneous trades and protocol discipline are onerous and for potential new entrants into that market it can be a daunting task to overcome.

Several brokers have solved this issue by offering FIX to arrowhead translation services to allow easy and ubiquitous trading, the downside being that such systems are very slow due to the amount of processing required to perform the translation into arrowhead and even more so in generating FIX compliant messages in the return path; this requires Persistence (storage of incoming FIX tags for later use) and Enrichment (calculation of values not available in arrowhead message such as Average Price).

What did Fixnetix do?

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Altera Stratix® V GX/GS PCIe Board with Dual QSFP+

BittWare's S5-PCIe (S5PE) is a PCIe x8 card based on the high-bandwidth, power-efficient Altera Stratix V GX or GS FPGA. 

For more information please contact Sarsen Technology on 01672 511166, or send us an email with your enquiry.

Altera Ships 20nm Arria 10 SoCs

Author - Laura

Altera has confirmed its leadership position in SoC FPGA products by shipping its second-generation SoC family. Arria® 10 SoCs are the industry’s only programmable devices that combine ARM® processors with a 20 nm FPGA fabric.

Embedded developers have a clear migration path with Altera for enhancing their next-generation systems. Arria 10 SoCs are fully software compatible with Altera’s previous 28 nm SoC product family allowing seamless software migration between generations. Arria 10 SoCs provide up to 50% higher performance and up to 4% lower power than the previous generation.

Altera SoC FPGAs enable smarter embedded systems by enabling single-chip product differentiation in both hardware and software. Combining ARM processors with FPGA fabric provides greater system value through reductions in power, costs and board space.

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Jeff Milrod, President and CEO of BittWare, says, "Altera’s Arria 10 is a true game changer. Native floating-point engines on these devices give system designers access to massive floating-point resources with tremendous ease-of-use and power efficiency in an FPGA. Classic signal processing applications can now interface analog signals directly to Arria 10 and process them there in floating point. For HPC and acceleration applications, FPGA algorithms no longer need to be ported to fixed point, nor do they need to be inefficiently implemented in fixed-point emulation of floating point. The Arria 10's native floating point provides more than 40 GFLOPS/W with a higher Fmax, while using only one-third of the logic resources. It is easier to use, lower power, faster, and less resource-intensive than any other alternative previously available.”

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For more information please contact Sarsen Technology - CONTACT US