Accelerate your 5G and NFV Workloads with Intel PAC and Netcope P4

Did you know, Netcope P4 supports Intel® FPGA PAC N3000?

Netcope P4 compiles the packet processing program written in open-standard P4 language into 100 Gbps FPGA firmware, allowing unprecedented flexibility and rapid development of high-speed network applications.

Netcope P4 Flyer 

It offers a revolutionary way for programmable network adapters to be easily programmed using P4 language without expert knowledge of hardware architecture, which can significantly save money when hiring dedicated firmware designers. It also shortens time-to-market, avoiding lengthy firmware development cycles.

Using the Arria 10 FPGA, now in mass production, Intel® FPGA PAC N3000 is the platform of choice for the acceleration of many bandwidth and latency-sensitive virtualised network applications, such as vRAN, vEPC, vBNG and others. Netcope P4 brings the possibilities for this card to a whole new level. Instead of tedious and error-prone HDL coding, the card can be programmed in the open-standard P4 language.

Netcope P4 is now specifically optimised to take advantage of the N3000 unique features, offering large capacities of lookups in off-chip DDR memories and achieving line-rate packet processing with low latency and resource utilization. With Netcope P4 and N3000, your fully custom 100 Gbps packet processor built with COTS hardware is just hours away.

Sarsen Technology is Netcope's UK partner. For more information on P4 or FPGA acceleration please contact us.

Watch Video - Intel® FPGA PAC N3000

ISC High Performance 2017 - Meet with BittWare and Sarsen Technology

Event: ISC 2017
Date: Sunday 18 June - Thursday 22nd June
Location: Frankfurst, Germany
Stand: A-1431

ISC High Performance is an international event for academic, industrial and commercial disciplines to come together and share ideas and knowledge across the entire high performance computing spectrum.

The 2017 conference offers 3 days of speakers and seminars based around this years focus topics:

HPC Systems	HPC Applications & Algorithms	HPC Trends & Challenges
Exascale System Developments (Architecture & Concepts)	Life Sciences	High Performance Visualization
Processor Technologies for HPC and AI	Energy Exploration	Big Data Experiments & Big Data Analysis
Memory Outlook	Turbulences & Combustion	Quantum Annealing for Combinatorial Optimization Problems
Interconnects for HPC Systems	Advanced Material Science
Programming Models (Concepts for Exascale)	Algorithms for Extreme Scale in Practice
	Large Scale Engineering & Cloud Computing

Sarsen Technology works with BittWare to provide customers with high-performance FPGA solutions based on Intel Stratix 10/Arria 10 and Xilinx UltraScale/UltraScale+ FPGAs, for data centres, network packet processing and cyber security applications.

Sarsen Technology is exhibiting at ISC 2017 alongside BittWare and EMG2, you can find us at stand A1431. BittWare’s range of Intel and Xilinx FPGA PCIe boards will be on display, along with live demos including Deep Learning with their OpenCL Board Support Package and 100 GbE packet processing with Intel’s DPDK.

For more information please contact Sarsen Technology.

BittWare Set To Launch New Networking Product at RSA 2017

StreamSleuth from BittWare is a brand new 100GbE packet processing appliance with a pre-programmed FPGA that performs hardware accelerated network packet processing at line rate.

• Use modes include packet broker, active monitor, or supplemental firewall.

• Users configure the device with a web-based GUI or API - no FPGA programming required!

StreamSleuth is the first product from the new BittWare Network Products group, focused on high-performance networking products.

You can meet with the BittWare team at the RSA Conference, Stand S312 - 13-17 Feb

RSA Conference
The current state of cybersecurity means there are many opportunities for the industry as a whole to collaborate on new innovations. Discovering the next great opportunity will require everyone to embrace new and unique perspectives from a broadly diverse base of people and sources.

RSA Conference’s mission is to connect you with the people and insights that will empower you to stay ahead of cyber threats.

For more information please contact Sarsen Technology on +44 1672 511166 or send us an email - info@sarsen.net

BittWare and nCk Research Collaborate to Provide an FPGA-based 100G Network Packet Broker with PCAP Filtering

As one of the market leading manufacturers in their field, new announcements from BittWare are always exciting...

The latest from the BittWare team in Concord, NH, is a collaboration with nCk Research - an innovative supplier of FPGA IP. This dream team have worked together to come up with a 100G network packet broker with PCAP filtering, which is implemented on BittWare's new PCIe board featuring Xilinx's UltraScale Virtex FPGA.

BittWare XUSP3S - Xilinx UltraScale 3/4-Length PCIe Board with Quad QSFP, DDR4, QDR-IV, and QDR-II+

PCAP processing expressions are used by many packet broker systems, but the point-to-point fabric from nCk Research is the first in the industry to optimise user inputs before loading resource settings into registers in the FPGA. This optimisation allows more rules to be packed into a smaller space and increases packet processing efficiency. The packet broker IP also provides configurable support for RMON1, line rate policies, aggregation, decimation, and de-duplication.

The XUSP3S is backward compatible with 10G/40G, and with nCk's IP supports up to 4x 100G ports and/or up to 16x 10/25G ports on each board. It can also be configured to implement any combination in between, allowing users to deploy with some 10G today and easily upgrade to all 100G in the field.


"We're pleased to be able to work with nCk to add innovative and comprehensive application IP to our already well established FPGA platforms," said Ron Huizen, Vice President of Systems & Solutions at BittWare.
"Their advanced filter IP component lets programmers use standard PCAP syntax to filter packets at full 100G line rate, and they can modify the filters on the fly- without having to reconfigure the FPGA. This, combined with nCk's other packet processing IP running on the most advanced FPGAs in the world, creates a compelling solution."


"FPGAs are the ideal choice for 100G at full line rate, and we're pleased to be able to partner with BittWare to build on their best-in-class FPGA platforms," said Matthew Chabot, President of nCk Research. "Their XUSP3S UltraScale board with support for quad 100G is a perfect fit."

Learn more:
10/25/40/100G Ethernet Filter IP Core for FPGA 
10/25/40/100G Packet Broker with PCAP Filtering 



Terabox
Up to 8 XUSP3S application cards can be installed in a BittWare TeraBox 4U rackmount system to handle up to 32x 100G ports and/or up to 128x 10/25G ports, allowing users to build virtually any packet processing solution with nCk network IP libraries; coupled with an optional PCIe DMA or NIC interface, it becomes possibly the most feature rich packet processing appliance in the industry.

Packet Broker with PCAP Filtering IP & Appliance Pricing and Availability
This configuration is available for purchase now, please contact Sarsen Technology for more information.