Showing posts with label terabox. Show all posts
Showing posts with label terabox. Show all posts

Friday, 25 November 2016

PCIe Board with Intel (Altera) Arria 10 GX FPGA Machine Learning Demonstration


BittWare took part in Super Computing 2016 last week, and used the event to showcase their must-see FPGA demos in network packet processing (NPP) and high-performance computing (HPC). If you were at the show you will also have seen BittWare's wide range of the latest Intel (formerly Altera) and Xilinx FPGA-based boards on display.



One of the demonstrations featured BittWare’s A10PL4 board, using Intel’s deep learning IP core loaded on the Arria 10 FPGA.

The A10PL4 from BittWare is an Altera Arria 10 FPGA PCIe board offering plenty of high speed serial I/O interfaces and debug support. Two QSFP cages are available, both connected to the Arria 10 FPGA removing latency in the external PHYs. The A10PL4 supports up to 32GB of DDR4 as well as flash memory with factory default and support for multiple FPGA images.


 
Machine Learning

'Machine Learning' is based on the development of computer programs that can learn and create their own rules. In deep learning, a task can be learned by the machine from a vast amount of data, either in supervised or unsupervised manner.

With the Deep Learning IP customers can leverage Intel Caffe in the Data Analytics Acceleration Library (DAAL) and Intel MKL-DNN to build AlexNet- or GoogleNet-like topologies without requiring a recompilation of the FPGA.

Accelerating machine learning applications like these are an excellent fit for FPGAs and OpenCL. Up to 16 A10PL4s can be combined inside a 4U server for a total of 18M logic elements and 512 GBytes of DDR4 memory.

Find out more - Terabox

For more information please speak to one of our FPGA specialists - +44 1672 511166 or send us an email - info@sarsen.net 



Tuesday, 15 March 2016

BittWare and nCk Research Collaborate to Provide an FPGA-based 100G Network Packet Broker with PCAP Filtering


As one of the market leading manufacturers in their field, new announcements from BittWare are always exciting...


The latest from the BittWare team in Concord, NH, is a collaboration with nCk Research - an innovative supplier of FPGA IP. This dream team have worked together to come up with a 100G network packet broker with PCAP filtering, which is implemented on BittWare's new PCIe board featuring Xilinx's UltraScale Virtex FPGA.

BittWare XUSP3S - Xilinx UltraScale 3/4-Length PCIe Board with Quad QSFP, DDR4, QDR-IV, and QDR-II+


PCAP processing expressions are used by many packet broker systems, but the point-to-point fabric from nCk Research is the first in the industry to optimise user inputs before loading resource settings into registers in the FPGA. This optimisation allows more rules to be packed into a smaller space and increases packet processing efficiency. The packet broker IP also provides configurable support for RMON1, line rate policies, aggregation, decimation, and de-duplication.

The XUSP3S is backward compatible with 10G/40G, and with nCk's IP supports up to 4x 100G ports and/or up to 16x 10/25G ports on each board. It can also be configured to implement any combination in between, allowing users to deploy with some 10G today and easily upgrade to all 100G in the field.


"We're pleased to be able to work with nCk to add innovative and comprehensive application IP to our already well established FPGA platforms," said Ron Huizen, Vice President of Systems & Solutions at BittWare.
"Their advanced filter IP component lets programmers use standard PCAP syntax to filter packets at full 100G line rate, and they can modify the filters on the fly- without having to reconfigure the FPGA. This, combined with nCk's other packet processing IP running on the most advanced FPGAs in the world, creates a compelling solution."


"FPGAs are the ideal choice for 100G at full line rate, and we're pleased to be able to partner with BittWare to build on their best-in-class FPGA platforms," said Matthew Chabot, President of nCk Research. "Their XUSP3S UltraScale board with support for quad 100G is a perfect fit."

Learn more:
10/25/40/100G Ethernet Filter IP Core for FPGA 
10/25/40/100G Packet Broker with PCAP Filtering 



Terabox
Up to 8 XUSP3S application cards can be installed in a BittWare TeraBox 4U rackmount system to handle up to 32x 100G ports and/or up to 128x 10/25G ports, allowing users to build virtually any packet processing solution with nCk network IP libraries; coupled with an optional PCIe DMA or NIC interface, it becomes possibly the most feature rich packet processing appliance in the industry.

Packet Broker with PCAP Filtering IP & Appliance Pricing and Availability
This configuration is available for purchase now, please contact Sarsen Technology for more information.

Tuesday, 7 October 2014

BittWare Currently Exhibiting at MILCOM 2014

Author: Laura Biddiscombe

Event: MILCOM 2014 - Find out more
Location: Baltimore Convention Center - Baltimore, MD
Date: October 06. 2014 - October 08. 2014

It's not too late to catch BittWare in Baltimore, MD, at the 33rd MILCOM event.
Attracting decision-makers from government, military, academia, and industry, MILCOM gathers military and government communications subject matter experts from around the globe to conduct in-depth discussions about the latest in technology advancements. This event is an ideal forum for industry to demonstrate the application of these technologies and to promote products and services that provide reliable solutions to today’s mission-critical challenges. Hundreds of technologies and solutions are being demonstrated right now.

BittWare are currently showcasing a host of their Altera FPGA-based hardware, including:

The Terabox - Integrated FPGA PCIe Platform
  • 20 TeraFLOPS processing: 16x Altera Stratix V GX/GS FPGAs
  • 1.28 Terabits/sec I/O
  • 6.5 Terabits/sec memory bandwidth
  • 4U or 5U Rackmount PCIe system (server, industrial, or expansion)
and the Channelizer – Integrated FPGA 6U VPX Platform
  • 19” 2U rackmount enclosure
  • 1-slot backplane
  • BittWare Stratix V FPGA-based 6U VPX board
  • 4-channel, up to 5 GSPS, 8-bit ADC
  • 2-channel, 5.6 GSPS, 14-bit DAC
  • 6U VPX rear transition module for access to VPX I/O

Join BittWare on Booth #419 at MILCOM until October 8 in Baltimore...