BittWare Releases Arria 10 OpenCL BSPs for Altera OpenCL SDK 16.0.2 Release

BittWare has recently announced the availability of Arria 10 FPGA Board Support Packages (BSPs) for Altera's recently released OpenCL SDK 16.0.2, including support for production silicon.

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BittWare’s OpenCL BSPs allow customers to develop applications for the Altera Arria 10 1150GX FPGA using OpenCL quickly and easily. OpenCL makes FPGA development much simpler by enabling designers to code their systems and algorithms in a high-level C-based framework, directly generating FPGA programming files from a pure software development flow.

FPGAs can dramtically improve speed and increase responsiveness for many system designs, in markets as diverse as defense/aerospace, fintech and life sciences. BittWare offers BSP variants to support High Performance Computing (HPC) as well as Network Processing applications.


"We've worked closely with Altera to ensure that our OpenCL BSPs provide the best quality results possible," said Chad Hamilton, BittWare VP of IP, Software & Support. "For those customers who prefer to code in a C-based framework, our OpenCL BSPs provide the tools necessary to get them up and running quickly and efficiently."

OpenCL Developers Bundle
The BittWare OpenCL BSPs are included in the OpenCL Developer’s Bundle, which includes a BittWare Arria 10 or Stratix V PCIe board, the BittWorks II system development software, the Altera Quartus II soft­ware, and the Altera SDK for OpenCL. This competitvely priced development bundle gives developers access to the latest generation of high-performance FPGAs on a validated PCIe board, while also significantly reducing their time ­to market by using OpenCL to develop their application.

Benefits of OpenCL for FPGAs

• Faster time-to-market using the OpenCL C-based parallel programming language as opposed to low-level hardware description language (HDL)
• Quick design exploration by working at a higher level of design abstraction
• Easy design re-use by re-targeting existing OpenCL C code to current and future FPGAs
• Faster design completion by generating an FPGA implementation of OpenCL C code in a single step, bypassing the manual timing closure efforts and implementation of communication interfaces between the FPGA, host, and external memories.
• Increased performance by offloading performance- intensive functions from the host processor to the FPGA
• Significantly lower power than a GPU or multicore CPU by using the Altera SDK for OpenCL, which generates only the logic needed