Hurrah! Next up, We Wish You a Merry Christmas.......
Sarsen Technology is an industry leading distributor of embedded hardware and software technology solutions. We specialise in single board computing, FPGA, digital signal processing, data acquisition and high-speed data recording COTS technology. Our clients are Europe's leaders in the telecommunications, defence, instrumentation, research, transportation and aerospace markets. You can find our web site at www.sarsen.net and follow us on Twitter at @Sarsen_Tech.
Wednesday, 12 December 2012
The Twelve Days of Christmas. Sarsen Style.
Hurrah! Next up, We Wish You a Merry Christmas.......
Wednesday, 5 December 2012
BittWare's Anemone - A New Approach to Floating Point DSP
It’s a word that is quite often mis-pronounced.
It’s not Ane-No-Me. Or worse – An-En-ema. Definitely not that!
BittWare’s first generation Anemone chip, the Anemone104 (AN104) is a completely scalable multicore processor with 16 eCores that provide a total sustained performance of 19.2 GFLOPS while consuming only 1 Watt of core power.
Featuring the Epiphany architecture from Adapteva, the BittWare Anemone combines the best assets of both FPGA and floating point DSP technology, thereby offering a completely new approach to floating point digital signal processing. The FPGA handles all the memory, I/O interfacing, protocol processing, and special functions, in addition to any computational tasks it may perform. This leaves the Anemone free to perform the complex processing tasks that DSPs are ideal for.
The AN104 features an internal high-throughput mesh network, with separate data paths for on-chip and off-chip communications. Total on-chip, inter-core bandwidth is 76.8 GBytes/sec full duplex, with an additional 8 GBytes/sec of off-chip bandwidth.
The BittWare Anemone Evaluation Kit provides a cost-effective way to begin evaluating the Anemone co-processor for FPGAs, featuring an Anemone104 and Altera Stratix III FPGA based evaluation board - ready to use out of the box, with the Ubuntu Linux OS and Anemone development tools installed on an included laptop.
Tuesday, 10 July 2012
High Frequency Trading speak to CEO Jeff Milrod about BittWare's FPGA development for the Low-Latency Financial Market
Thursday, 29 March 2012
March Edition of News Bytes now online

The March 2012 edition of News Bytes includes news stories on BittWare Anemone™ Co-Processor for FPGA Boards, The Low-Latency Summit for financial trading 2012, Wildcat PCI-104 SBC with Intel Core 2 Duo processor, MIL-COTS LCD Touchscreen Monitor With Sealed Keyboard, United Electronics Industries (UEI) to Exhibit at ITEC 2012, Conduant SNAP12 Optical FPGA Card, BittWare BittWorks II Release Notes and Electronic Engineering Journal: Reducing Power Consumption and Increasing Bandwidth on 28-nm FPGAs.
Link to the March News Bytes Newsletter:
Monday, 17 October 2011
BittWare International Sales Conference 2011
Nigel, Robbie & Tim travelled to Concord, NH at the end of September for BittWare's 2011 International Distributor Sales & Traing Conference. We learnt about lots of new exciting technology including the Altera Stratix V COTS hardware & the new Anemone FPGA Co-Processor. We also travelled one evening to the Castle in the Clouds in the White Mountains in New Hampshire where the photo above was taken.
Tuesday, 3 May 2011
BittWare Anemone - A New Approach to Floating Point DSP

Traditional floating point DSPs, while excellent at complex processing tasks, have limitations when it comes to chip real estate and power efficiency that have caused them to become an endangered species. And FPGAs, while superior for versatility and configurability, can be difficult to use for complex and evolving applications. The BittWare Anemone, featuring the Epiphany architecture from Adapteva, enables the best assets of both to be combined, thereby offering a completely new approach to floating point digital signal processing. This hybrid solution provides a standard processor software development environment working in conjunction with a world-class FPGA platform, allowing users to optimally partition their algorithms into hardware and software. The result is superior development productivity and unmatched system size, weight, and power.






