BittWare to Exhibit at SIFMA 2012

June 19-20, 2012         Hilton New York

The Securities Industry and Financial Markets Association (SIFMA) Tech Expo draws the top technology exhibitors providing services to the financial services industry. It brings together the shared interests of hundreds of securities firms, banks and asset managers. These companies are engaged in communities across the country to raise capital for businesses, promote job creation and lead economic growth.

BittWare has designed and developed a family of PCIe format Altera Stratix V FPGA hardware optimised for the financial trading market.  Ron Huizen, Darren Taylor and Chad Hamilton from BittWare will be exhibiting at SIFMA next week on booth #1823, showcasing their (growing) Stratix V family of PCIe cards.  

More than 70 senior regulators and industry experts will participate in 29 educational sessions on the foremost issues facing financial technologists, and the event is expected to bring together more than 4,000 industry-leading professionals to discover the latest trends and solutions.

If you would like to visit BittWare at the SIFMA Tech Expo please give us a call on +44 1672 511166 to arrange a time.

Please contact Sarsen Technology for full details of the full range of PCIe format Altera Stratix V FPGA hardware and software developed for this market. E - info@sarsen.net 

http://www.sarsen.net/dept/financial-trading_d0145.htm

Low-Latency Summit London 2012

Tim Norris, Robbie Burns & Nigel Norman participated in the Low-Latency Summit for High Frequency Financial Trading yesterday. Altera showcased a BittWare S5-PCIe Altera Stratix V FPGA PCIe format board on their booth. Burkhard Jour represented BittWare at the event organised the by the A-Team Group. The event was held at America Square Conference Centre and highlighted the issues around implementing new technologies such as large FPGAs in the HFT market space. There was a good and informed attendance. There was also a nice contrast between high technology such as the Altera Stratix V FPGA with 3.9 billion gates and the 2000 year old Roman wall next to the exhibition space.

Link to the Low-Latency Summit web site:

Low-Latency Summit 2012