Author - Laura
The Altera SDK for OpenCL has been selected by Electronics Weekly as its design tool of the year at the annual Elektra European
Electronics Industry Awards gala in London. This award is the latest in a series of recognitions the Altera SDK for
OpenCL has received since its release in 2012.
Altera offers the
industry’s only OpenCL-conformant solution in today's market that allows software
programmers to easily implement OpenCL applications on FPGA
accelerators.
Founded by
Electronics Weekly
in 2003, the
Elektra European Electronics Industry Awards are the most prestigious product, technology and business awards in Europe, recognising the achievements of individuals
and companies in the electronics industry. A panel of independent industry experts and representatives
from
Electronics Weekly selected the Altera SDK for OpenCL as the winner in its "Design Tools and Development Software” category.
Read Full Press Release
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BittWare’s OpenCL Developer’s Bundle provides the tools necessary to
begin developing applications for the Altera Stratix V using OpenCL.
OpenCL dramatically simplifies FPGA development by enabling designers to
code their systems and algorithms in a high-level C-based framework,
directly generating FPGA programming files from a pure software
development flow.
The OpenCL Developer’s Bundle includes BittWare’s
S5-PCIe-HQ (S5PH-Q)
half-length PCIe board, the BittWorks II system development software,
the Altera Quartus II software, and the Altera SDK for OpenCL. This
development bundle gives developers access to the latest generation of
high-performance FPGAs on a validated COTS PCI Express board, while also
significantly reducing their time-to-market by using OpenCL to develop
their application.
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About the Altera SDK
The
Altera SDK for OpenCL allows programmers to develop
algorithms with the OpenCL language and harness the performance and
power efficiencies of FPGAs. The Altera SDK for OpenCL includes a rapid
prototyping design flow that allows OpenCL kernel code to be emulated,
debugged, optimized, profiled and re-compiled to a hardware
implementation in minutes. The re-compiled kernels can be tested and run
on an FPGA immediately, saving programmers weeks of development time.
