In Review: Xilinx SDSoC and Levels of Abstraction

The SDSoC development environment from Xilinx provides engineers and developers using Zynq SoC and MPSoC with a familiar C/C++ design environment, including a straightforward Eclipse IDE, expanded library, board, and design services ecosystem support.

In a recent article posted on the Xilinx blog, Part 196 of Adam Taylor's MicroZed Chronicles takes a good look at what SDSoC is, how it works and the benefits gained from using it.

Adam Taylor’s MicroZed Chronicles, Part 196: SDSoC and Levels of Abstraction

Originally posted by Xilinx Employee sleibso ‎05-22-2017 09:40 AM - edited ‎05-22-2017 10:28 AM 
Re-posted with permission.

We have looked at SDSoC several times throughout this series, however I recently organized and presented at the NMI FPGA Machine Vision event and during the coffee breaks and lunch, attendees showed considerable interest in SDSoC - not only for its use in the Xilinx reVISION acceleration stack but also its use in a range of over developments. As such, I thought it would be worth some time looking at what SDSoC is and the benefits we have previously gained using it. I also want to discuss a new use case.

SDSoC Development Environment

SDSoC is an Eclipse-based, system-optimizing compiler that allows us to develop our Zynq SoC or Zynq UltraScale+ MPSoC design in its entirety using C or C++. We can then profile the application to find aspects that cause performance bottlenecks and move then into the Zynq device’s Programmable Logic (PL). SDSoC does this using HLS (High Level Synthesis) and a connectivity framework that’s transparent to the user. What this means is that we are able develop at a higher level of abstraction and hence reduce the time to market of the product or demonstration.

To do this, SDSoC needs a hardware platform, which can be pre-defined or custom. Typically, these platforms within the PL provide the basics: I/O interfaces and DMA transfers to and from Zynq device’s PS’ (Processing System’s) DDR SDRAM. This frees up most the PL resources and PL/PS interconnects to be used by SDSoC when it accelerates functions.

This ability to develop at a higher level and accelerate performance by moving functions into the PL enables us to produce very flexible and responsive systems. This blog has previously looked at acceleration examples including AES encryption, matrix multiplication, and FIR Filters. The reduction in execution time has been significant in these cases. Here’s a table of these previously discussed examples:

For more information on Xilinx Zynq MPSoC based hardware, the SDSoC environment or embedded computing in general please get in touch with the knowledgeable team at Sarsen Technology - info@sarsen.net

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